PULSE AND DIGITAL CIRCUITS
Group A

Combinational Logic

Boolean algebra: Introduction, postulates of Boolean algebra, fundamental theorems,
uniqueness properties, laws of Boolean algebra, De Morgan's theorem, the (inclusion)
implication relation, bounds of Boolean algebra, duality in Boolean algebra, Boolean
constants, variables and functions, two-valued Boolean algebra switching algebra, electronic
gates and mechanical contacts.
Boolean functions and logic operations: Introduction, the normal form, the canonical form,
fundamental products and sums, disjunctive and conjunctive normal forms, binary, octal and
hexadecimal, designations, self-dual functions, logical operations, NAND and NOR
operations, EXCLUSIVE-OR operation, functionally complete sets.
Minimization of switching functions: The Karnaugh map-introduction cubes and the
Karnaugh map, prime cubes, maximum sum of products, minimum product of sums, don't
care forms, five- and six-variable maps, multiple output minimization.
Tabular methods of minimization: Introduction, Quine-McCluskey algorithm, the
dominance relation cyclic functions, the degree of adjacency and essential prime cubes.
Logic synthesis of switching functions: Introduction, AND, OR and inverter networks,
NAND and NOR networks, EXCLUSIVE-OR networks, multiplexers, read only memories,
programmable logic arrays (PLA), PLA minimization, essential prime cube theorems, PLA
folding.
Reliable design and fault detection tests: Introduction, fault classes and models, fault
diagnosis and testing, test generation, fault table method, path sensitization method, Boolean
difference method, reliability through redundancy, hazards and hazard-free designs, quaded
logic.

 

Group B


Sequential Circuits
Introduction to synchronous sequential circuits, the finite-state model-basic definitions, the memory elements and their excitation functions-S-R flip-flop, J-K flip-flop,D flip-flop, T
flip-flop, synthesis of synchronous sequential circuits.

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Capabilities, minimization and transformation of sequential machines, the finite-state modelfurther
definitions, capabilities and limitations of finite-state machines, state equivalence and machine minimization, simplification of incompletely specified machines compatible states, the non-uniqueness of minimal machines, closed set of compatibles. The compatible graph and the merger table.
Asynchronous sequential circuits. Fundamental mode circuits, synthesis, state assignments
in asynchronous sequential circuits, pulse mode circuits.

 

Finite state recognizers: Deterministic recognizers, transition graphs, converting nondeterministic into deterministic graphs, regular expressions, transition graphs recognizing regular sets, regular sets corresponding to transition graphs.


 




 

 

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